Таблицы трансляции виртуальной памяти

[Frozenfoot]

Здравствуйте!

Не мог бы кто-нибудь помочь со следующей задачей. Необходимо перевести процессор в защищённый режим, сделать тождественную трансляцию 64Гб памяти, перевести процессор в Long mode. Компилятор - fasm. Программа будет запускаться в Bochs 2.6.8, ОС - Dos 6.22. Пытался модифицировать код из книги Программирование на ассемблере на платформе x86-64, зациклив выделение страниц - не получилось, эмулятор перезагружается. Заранее благодарен за любую оказанную помощь.

Файл LM_CODE.asm:

;---------------------------
; Processor in long mode
; stack pointer = 08000h
; avail virtual memory 0h-200000h
;---------------------------

PLM4_BASE_ADDRESS equ 100000h

LM_CODE_START:
	mov rdi, PLM4_BASE_ADDRESS
	call ZeroPage_4K

	

	jmp $


message db "Long mode!",0

OutText:
;IN
;  RSI - ZS offset
;  AL  - col
;  AH  - row
;  BL  - char attributes
	push rdx
	xor rdx, rdx
	mov edx, 0B8000h
	call OutTextEx
	pop rdx
	ret

OutTextEx:
;IN
;  RSI - ZS offset
;  AL  - col
;  AH  - row
;  BL  - char attributes
;  RDX - text buffer

	push rax
	push rdi
	push rsi
	push rbx

	xor rdi, rdi
	push rax
	shr rax, 8
	and rax, 0FFh
	imul rdi, rax, 160
	pop rax
	and eax, 0FFh
	shl rax, 1
	add rdi, rax
	add rdi, rdx

      .rep:
	cmp byte [rsi],0
	jz .end
	mov bh, byte [rsi]
	mov byte [rdi], bh
	inc rdi
	mov byte [rdi], bl
	inc rdi
	inc rsi

	jmp .rep
       .end:

	pop rbx
	pop rsi
	pop rdi
	pop rax
	ret

NextAvail4KPage dd 1  ; next avail page for table for virt addr translation

AllocPage_4K:
;IN
;   RAX physical address low 12 bits must be clear
;   RBX virtual address  low 12 bits and high 16 bits must be clear
	push rax
	push rbx
	push r8
	push rdi
	push rdx
	push r9
	push r10
	push r11
	push r12    ; save all using registers

	mov r12, rax	  ; r12 = phys addr

	mov r8, rbx
	shr r8, 39  ; r8 = index in PML4

	shl r8, 3   ; r8 = offset in PML4
	add r8, PLM4_BASE_ADDRESS ; r8 = PML4 entry addr
	mov r9d, [r8+4]
	shl r9, 32
	mov r9d, [r8]		  ; r9 = PML4 entry
	mov eax, r9d		  ; eax = r9d
	and eax, 1		  ; checking present flag
	jz @f
	jmp .setPDPE
       @@:
		    ; if PDP not presented then alloc PDP table
	xor rdi, rdi
	mov edi, [NextAvail4KPage]
	shl rdi, 12    ; rdi = next avail page addr
	add rdi, PLM4_BASE_ADDRESS
	call ZeroPage_4K

	mov rax, rdi		   ; rax = new PDP table
	or eax, 3		   ; rax = PDP table addr or Present or Write
	mov rdx, rax		   ; rdx = rax

	mov [r8], eax
	shr rax, 32
	mov [r8+4], eax
	inc dword [NextAvail4KPage]
	mov r9, rdx		   ;
       .setPDPE:		   ;r9 = PML4 entry
	;-------------------------------------------------------
	and r9d, 0FFFFF000h	   ; r9 = PDP table addr
	mov r8, rbx
	shr r8, 30
	and r8d, 1FFh		   ; r8 = index in PDP
	shl r8, 3		   ; r8 = offset in PDP
	add r8, r9		   ; r8 = PDP entry addr
	mov r10d, [r8+4]
	shl r10, 32
	mov r10d, [r8]		   ; r10 = PDP entry
	mov eax, r10d		   ; eax = r10d
	and eax, 1		   ; checking present flag
	jz @f
	jmp .setPDE
       @@:
		 ; if PDPE not presented then alloc PD table
	xor rdi, rdi
	mov edi, [NextAvail4KPage]
	shl rdi, 12    ; rdi = next avail page addr
	add rdi, PLM4_BASE_ADDRESS
	call ZeroPage_4K

	mov rax, rdi
	or eax, 3		   ; rax = PD table addr or Present or Write
	mov rdx, rax

	mov [r8], eax
	shr rax, 32
	mov [r8+4], eax
	inc dword [NextAvail4KPage]
	mov r10, rdx		   ; r10 = PDP entry
       .setPDE: 		   ; r10 = PDPE
	;----------------------------------------------------------
	and r10d, 0FFFFF000h	   ; r10 = PD table addr

	mov rdx, rbx
	shr rdx, 21
	and edx, 1FFh		   ;
	xor r8, r8
	mov r8d, edx		   ; r8 = index in PD
	shl r8, 3		   ; r8 = offset in PD
	add r8, r10		   ; r8 = PD entry addr

	mov r11d, [r8+4]
	shl r11, 32
	mov r11d, [r8]		   ;
	mov eax, r11d		   ; eax = r10d
	and eax, 1		   ; checking present flag
	jz @f
	jmp .setPTE
       @@:
	xor rdi, rdi
	mov edi, [NextAvail4KPage]
	shl rdi, 12    ; rdi = next avail page addr
	add rdi, PLM4_BASE_ADDRESS
	call ZeroPage_4K

	mov rax, rdi
	or eax, 3		   ; rax = PT addr or Present or Write
	mov rdx, rax

	mov [r8], eax
	shr rax, 32
	mov [r8+4], eax
	inc dword [NextAvail4KPage]
	mov r11, rdx		   ; r11 = PD entry
       .setPTE:
	;------------------------------------------------------------
	and r11d, 0FFFFF000h	   ; r11 = PT addr

	mov rdx, rbx
	shr rdx, 12
	and edx, 1FFh
	xor r8, r8
	mov r8d, edx		   ; r8 = index in PT
	shl r8, 3		   ; r8 = offset in PT
	add r8, r11		   ; r8 = PT entry addr

				   ; r12 = phys addr
	or r12d, 3		   ; page addr or present or write
	mov [r8], r12d
	shr r12, 32
	mov [r8+4], r12d

	pop r12
	pop r11
	pop r10
	pop r9
	pop rdx
	pop rdi
	pop r8
	pop rbx
	pop rax
	ret

AllocPage_2M:
;IN
;   RAX physical address low 21 bit must be clear
;   RBX virtual address  low 21 bit high 16 bits must be clear
	push rax
	push rbx
	push r8
	push rdi
	push rdx
	push r9
	push r10
	push r12    ; save all using registers

	mov r12, rax	  ; r12 = phys addr

	mov r8, rbx
	shr r8, 39  ; r8 = index in PML4

	shl r8, 3   ; r8 = offset in PML4
	add r8, PLM4_BASE_ADDRESS ; r8 = PML4 entry addr
	mov r9d, [r8+4]
	shl r9, 32
	mov r9d, [r8]		  ; r9 = PML4 entry
	mov eax, r9d		  ; eax = r9d
	and eax, 1		  ; checking present flag
	jz @f
	jmp .setPDPE
       @@:
		    ; if PDP not presented then alloc PDP table
	xor rdi, rdi
	mov edi, [NextAvail4KPage]
	shl rdi, 12    ; rdi = next avail page addr
	add rdi, PLM4_BASE_ADDRESS
	call ZeroPage_4K

	mov rax, rdi		   ; rax = new PDP table
	or eax, 3		   ; rax = PDP table addr or Present or Write
	mov rdx, rax		   ; rdx = rax

	mov [r8], eax
	shr rax, 32
	mov [r8+4], eax
	inc dword [NextAvail4KPage]
	mov r9, rdx		   ;
       .setPDPE:		   ;r9 = PML4 entry
	;-------------------------------------------------------
	and r9d, 0FFFFF000h	   ; r9 = PDP table addr
	mov r8, rbx
	shr r8, 30
	and r8d, 1FFh		   ; r8 = index in PDP
	shl r8, 3		   ; r8 = offset in PDP
	add r8, r9		   ; r8 = PDP entry addr
	mov r10d, [r8+4]
	shl r10, 32
	mov r10d, [r8]		   ; r10 = PDP entry
	mov eax, r10d		   ; eax = r10d
	and eax, 1		   ; checking present flag
	jz @f
	jmp .setPDE
       @@:
		 ; if PDPE not presented then alloc PD table
	xor rdi, rdi
	mov edi, [NextAvail4KPage]
	shl rdi, 12    ; rdi = next avail page addr
	add rdi, PLM4_BASE_ADDRESS
	call ZeroPage_4K

	mov rax, rdi
	or eax, 3		   ; rax = PD table addr or Present or Write
	mov rdx, rax

	mov [r8], eax
	shr rax, 32
	mov [r8+4], eax
	inc dword [NextAvail4KPage]
	mov r10, rdx		   ; r10 = PDP entry
       .setPDE: 		   ; r10 = PDPE
	;----------------------------------------------------------
	and r10d, 0FFFFF000h	   ; r10 = PD table addr

	mov rdx, rbx
	shr rdx, 21
	and edx, 1FFh		   ;
	xor r8, r8
	mov r8d, edx		   ; r8 = index in PD
	shl r8, 3		   ; r8 = offset in PD
	add r8, r10		   ; r8 = PD entry addr

				   ; r12 = phys addr
	or r12d, 010000011b	   ; page addr or PS or Present or Write
	mov [r8], r12d
	shr r12, 32
	mov [r8+4], r12d

	pop r12
	pop r10
	pop r9
	pop rdx
	pop rdi
	pop r8
	pop rbx
	pop rax
	ret

ZeroPage_4K:
;IN
;   RDI - 4K page addr for NULL
	push rdi
	push rax
	push rcx

	xor rax, rax
	mov rcx, 1000h/8
	rep stosq

	pop rcx
	pop rax
	pop rdi
	ret

[Frozenfoot]

Файл LM.asm

ORG 100h

     STACK_BASE_ADDRESS     equ 08000h
     PM_CODE_BASE_ADDRESS   equ 0100h
     PM_CODE_SIZE equ PM_CODE_END - PM_CODE_BASE_ADDRESS

     CODE_SELEKTOR  equ 8h
     DATA_SELEKTOR  equ 10h
     CODE64_SELEKTOR equ 18h

     PML4_addr equ 1FC000h
     PDPE_addr equ 1FD000h
     PDE_addr  equ 1FE000h

start:
     mov ax,3
     int 10h

     in  al,92h
     or  al,2
     out 92h,al

     xor eax, eax
     mov ax, cs
     shl eax,4
     add eax, PROTECTED_MODE_ENTRY_POINT
     mov [ENTRY_OFF],eax

     xor eax, eax
     mov ax,cs
     shl eax,4
     add eax, GDT

     mov dword [GDTR+2],eax
     lgdt fword [GDTR]

     cli
     in  AL,70h
     or  AL,80h
     out 70h,AL

     mov eax, cr0
     or  al,1
     mov cr0, eax

     db  66h
     db  0EAh
ENTRY_OFF dd PROTECTED_MODE_ENTRY_POINT
     dw  CODE_SELEKTOR

align 8
GDT:
	NULL_descr	db		8 dup(0)
	CODE32_descr	db		0FFh,0FFh,00h,00h,00h,10011010b,11001111b,00h
	DATA_descr	db		0FFh,0FFh,00h,00h,00h,10010010b,11001111b,00h
	CODE64_descr	db		00h, 00h,00h,00h, 00h,10011000b,00100000b,00h
	GDT_size	equ		$-GDT

label GDTR fword
		dw		GDT_size-1		
		dd		?

use32
PROTECTED_MODE_ENTRY_POINT:
	mov ax, DATA_SELEKTOR
	mov ds, ax
	mov es, ax
	mov ss, ax
	mov esp, STACK_BASE_ADDRESS

	call delta
   delta:
	pop ebx
	add ebx, PM_CODE_START-delta

	mov esi, ebx
	mov edi, PM_CODE_BASE_ADDRESS
	mov ecx, PM_CODE_SIZE
	rep movsb


	mov eax,PM_CODE_BASE_ADDRESS
	jmp eax


PM_CODE_START:
ORG PM_CODE_BASE_ADDRESS

	mov eax, cr4
	bts eax, 5   ; PAE = 1
	mov cr4, eax

	mov dword [PDE_addr], 010000011b	; PS or Present or Write
	mov dword [PDE_addr+4], 0
	mov dword [PDPE_addr], PDE_addr or 3	; Present or Write
	mov dword [PDPE_addr+4], 0
	mov dword [PML4_addr], PDPE_addr or 3	; Present or Write
	mov dword [PML4_addr+4], 0

	mov eax, PML4_addr
	mov cr3, eax

	mov ecx, 0xC0000080 ; EFER
	rdmsr
	bts eax,8  ; EFER.LME = 1
	wrmsr

	mov eax, cr0
	bts eax, 31 ; PG = 1
	mov cr0, eax

	jmp CODE64_SELEKTOR:LONG_MODE_ENTRY_POINT
use64
LONG_MODE_ENTRY_POINT:
	mov ax, ds  ; reload all segment registers
	mov ds, ax
	mov ss, ax
	mov es, ax

include 'LM_CODE.ASM'
PM_CODE_END:

[Frozenfoot]

Файл lmstructures.asm

;
;  Long mode struct defines
;

;MSR indexes
IA32_STAR  equ 0C0000081h
IA32_LSTAR equ 0C0000082h
IA32_FMASK equ 0C0000084h
IA32_EFER  equ 0C0000080h


INTGATE64 equ 1110b
TRAPGATE64 equ 1111b
CALLGATE64 equ 1100b
TSS64_type equ 1001b

macro DEFINE_GATE64 selector, offset, IST, gate_type, DPL
{
	dd (offset and 0FFFFh) or (selector shl 16)
	dd (8000h or (DPL shl 13) or (gate_type shl 8) or IST) or ((offset shr 16) and 0FFFFh)
	dd (offset shr 32)
	dd 0
}

macro DEFINE_TSS64Descr BaseAddress, Limit
{
	dd (Limit and 0FFFFh) or ((BaseAddress and 0FFFFh) shl 16)
	dd ((BaseAddress shr 16) and 0FFh) or (TSS64_type shl 8) or (8 shl 12) or (Limit and 0F0000h) or (BaseAddress and 0FF000000h)
	dd (BaseAddress shr 32)
	dd 0
}

macro DEFINE_INTGATE64 selector, offset, IST
{
	DEFINE_GATE64 selector, offset, IST, INTGATE64, 0
}

macro DEFINE_TRAPGATE64 selector, offset, IST
{
	DEFINE_GATE64 selector, offset, IST, TRAPGATE64, 0
}

macro DEFINE_CALLGATE64 selector, offset
{
	DEFINE_GATE64 selector, offset, 0, CALLGATE64, 0
}


struc TSS64
{
  .TSSBase:
  dd ?
  .RSP0 dq ?
  .RSP1 dq ?
  .RSP2 dq ?
  dq ?
  .IST1 dq ?
  .IST2 dq ?
  .IST3 dq ?
  .IST4 dq ?
  .IST5 dq ?
  .IST6 dq ?
  .IST7 dq ?
  dq ?
  dw ?
  .IOMapBase dw $-.TSSBase
}

[Frozenfoot]

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